Different types of memory are used in electronic apparatus for various purposes. Read-only memory (ROM) and random-access memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for powering-up an apparatus. ROM, however, cannot generally be changed. RAM, on the other hand, allows data to be written to, or read from, selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatus since, though it must be refreshed, it is less expensive and requires less chip space than SRAM. Though more expensive and space consuming, SRAM does not require refresh, making it faster. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants (PDAs).
A typical SRAM device is designed to store thousands of bits of information. These bits are stored in individual cells, organized as rows and columns to make efficient use of space on the semiconductor substrate on which the SRAM is fabricated. A commonly used cell architecture is known as the “6T” cell, by virtue of having six MOS transistors. Four transistors defining an SRAM cell core are configured as cross-coupled inverters, which act as a bistable circuit, indefinitely holding the state imposed onto it while powered. Each inverter includes a load transistor and a driver transistor. The output of the two inverters will be in opposite states, except during transitions from one state to another. Two additional transistors are known as “pass” transistors, which provide access to the cross-coupled inverters during a read operation (herein referred to as READ) or write operation (herein referred to as WRITE). The gate inputs of the pass transistors are typically connected in common to a “word line,” or WL. The drain of one pass transistor is connected to a “bit-line,” or BL, while the drain of the other pass transistor is connected to the logical complement of the bit-line, or BL_.
A WRITE to a 6T cell is effected by asserting a desired value on the BL and a complement of that value on BL_, and asserting the WL. Thus, the prior state of the cross-coupled inverters is overwritten with a current value. A READ is effected by first precharging both bitlines to a logical high state and then asserting the WL. In this case, the output of one of the inverters in the SRAM cell will pull one bitline lower than its precharged value. A sense amplifier detects the differential voltage on the bitlines to produce a logical “one” or “zero,” depending on the internally stored state of the SRAM cell.
A consideration in the design of the transistors in the SRAM cell is the geometric parameters of the transistors. The gate length and width determine in large part the speed and saturation drive current, IDsat, also known as the maximum drive current capacity of the transistors. Appropriate values of gate length and width of the six transistors of the 6T cell must be chosen to ensure that a read operation does not destroy the previously stored datum. Inappropriate transistor parameter values in conjunction with the BL and WL voltages applied during a READ may result in a change in state of the memory cell due to random asymmetries resulting from imperfections in the manufacturing process. The necessity to guard against such READ instability places an undesirable constraint on the design parameters of the transistors in the 6T cell, limiting the ability of the designer to increase READ performance of the SRAM while keeping within area and power constraints and maintaining the ability to write into the cell.
A constraint on the design of a 6T SRAM cell is that the pass gate is generally designed to be relatively weaker than the inverter driver transistor to ensure stability, but relatively stronger than the inverter load transistor to enable a WRITE. Also, for stability, the inverter load transistor cannot be too weak relative to the inverter driver transistor. Inverter transistors with relatively low threshold voltage (Vt), the voltage at which the transistor begins to conduct, may also degrade stability of the SRAM cell.
Prior art includes methods to assist the WRITE to allow the relatively weaker pass gate for good stability. This prior art includes pulling the BL below the SRAM low voltage supply, Vss, for WRITE, or providing a lower SRAM high voltage supply, VDD, to the inverters for WRITE relative to that for READ. However, the relatively weaker pass gate enabled by this prior art has the undesirable affect of degrading the read current.
Prior art also includes memory cells with separate ports for READ and WRITE that might at first seem to relax some of the constraints to allow a fast READ. However, such cells are generally relatively large. Also there is still the constraint of not upsetting the unaddressed cells in a selected row for WRITE in an array in which only a subset of the cells in a selected row are written into in a single WRITE cycle. The cells in the selected row that are not written into are subjected to bias conditions similar to that for a READ, and are subject to upset.
Accordingly, what is needed in the art is an SRAM cell design that relaxes the constraints on the SRAM cell transistor design parameters to enable higher speed SRAM designs with a relatively compact layout.